At present, heat sink manufacturing processes allow for a large design freedom. However, efficient design of these components remains challenging. As such, most designs are comprised of straight channels, or a periodic array of fins. In this contribution, we present topology optimization as a means for improving heat sink design for microelectronics cooling. A highly efficient fixed-point solver for the flow with low memory use enables the use of high-resolution numerical grids and topologically optimized designs. We present first results for microchip heat sinks and show optimized designs for a range of pressure drops and flow rates. The optimizations are carried out based on a 2.5D conjugate heat transfer model, where more than 4 million design variables are used, matching the design resolution with the manufacturing tolerance of chemical etching. For low pressure drops, the designs turn out as sparse arrays of fins arranged to form V shapes, whereas for high pressure drops, the fins are packed much more densely, but still arranged in a very structured way. Finally, we analyse the topologically optimized designs in full 3D simulations, and assess their performance compared to that of traditional heat sinks under similar design conditions. To that effect, we compare their friction factor, thermal resistance, among other engineering quantities of interest, showing significant improvements up to 50%.